SOE - Infi 90 Series INSEM01 | ABB - DCS Center

Microprocessor

The INTKM01 module uses a DSP 2101, provided with internal memory for program and data storage, a timer and a bidirec tional synchronous serial line. DSP 2101 uses an external BOOT EPROM containing the module firmware and an exter nal RAM. In addition, the module contains the circuits for bus and address management. BOOT EPROM This memory is used upon power-on by the microprocessor to load its internal program memory. In addition, in the EPROM there is the configuration data pertinent to the logic circuitry of the board. RAM The RAM memory with 16 kiloword size is used for external code memory. FIFO These two FIFO memories are used to transfer data between the I/O expander bus master (INSEM01) and the internal microprocessor. FIFO in is used to transfer the absolute time from INSEM01 module to the INTKM01 module in the initialization sequence. FIFO out is used to transfer the absolute time information from the microprocessor to the I/O expander bus master. The abso lute time is written on FIFO out every one millisecond. The size of each memory is 512 bytes.

IRIG-B Interface

These circuits allow the connection between the INTKM01 module and the signal coming from the external receiver through the NTST01 unit. The IRIG-B time codes are a group of rate-scaled serial time formats containing the time-of-year in binary coded decimal. This time information includes days, hours, minutes, seconds, tenths of seconds, and hundredths of seconds. The IRIG-B is transmitted every second and the INTKM01 module accepts it in the DC level shift format.

Sync Time Information Interface

This interface is used to generate the sync time information. It is transmitted every second to the NTST01 unit. The time infor mation is generated by the serial port of the processor and a synchro pulse is generated by an internal synchro circuit. The transmission of the sync time information to the NTST01 unit is performed in a RS-485 standard at 62.5 kilohertz. The NTST01 unit transmits to the INTKM01 module, through a RS-485 line. If the INTST01 unit is in a fault state or is not con nected, the INTKM01 module detects the absence of its NTST01 unit.

I/O Expander Bus Control

These circuits include the control circuit for the accesses from I/O expander bus and the communication circuit and FIFOs between the microprocessor and I/O expander bus master (INSEM01). The circuits contain the module address set in the module address switch, and generate the control signals in the various types of access from I/O expander bus.

Machine Fault Timer

The microprocessor continually retriggers the machine fault timer. If the microprocessor or the firmware fails the controller goes in fail state. The INSEM01 module reads this state and stops the module operations.

IMSED01 and IMSET01 Modules

The IMSED01 and IMSET01 modules acquire 16 digital inputs from the field, and are connected by NTDI01 or NTU-7I1 termi nation units. They communicate through the I/O expander bus with the controller for exchanging data and information for event synchronization. The IMSET01 module is also connected to the time-sync link by an NTST01 unit. One IMSET01 module and up to 63 IMSED01 modules can be supported by one con troller.

Functions

The IMSET01 and IMSED01 modules perform two functions: • The acquisition of the 16 digital inputs from the field. • The synchronization of their internal clocks. The IMSET01 module receives the time information from the time-sync link and keeps the internal clocks synchronized with this time. The two modules are controlled by the controller, and communicate across the I/O expander bus. The controller keeps the IMSED01 modules synchronized by reading the time from the IMSET01 module and writing it to the IMSED01 mod ules with a broadcast message.

Digital Inputs

The IMSET01 and IMSED01 modules can operate in two dis tinct modes: DI standard mode and sequence of events mode. • In DI standard mode the 16 digital inputs are acquired by using dedicated function codes 241 and 242 which control the 16 digital inputs as a function code 84. In DI standard mode the digital inputs have a filter on each input channel. It is possible to select two response times by jumper: fast (1.5 milliseconds) and slow (18 milliseconds). • In sequence of events mode all digital inputs are acquired every millisecond and compared to the previous value. If there is a change in one or more inputs, the new status is stored internally and placed in a FIFO_out buffer (Fig. 2-2), with its own time-stamp. A debounce procedure and a delay procedure are processed during acquisition. The debounce procedure ensures the valid ity of an input state change. A configuration parameter (DBFILT, unique for the 16 DI channels) determines the dura tion for which an input reading must remain stable to be accepted as a state change. The delay procedure compensates for the delay time in switching from zero to one (T on) or from one to zero (T off) for each channel. T on and T off are configu ration parameters for each channel. The delay is the estimated delay between the occurrence of the physical event and the time at which the event has been detected. It is estimated on the basis of characteristics of the acquisition equipment, it can be different for transition from zero to one and for transition from one to zero. In addition, each digital input can be configured out of scan. A state change of an out of scan digital input is not placed in the FIFO_out.